Analog-to-digital converters can be implemented with different topologies. In particular, interleaved and pipelined analog-to-digital converters require gain stages which need to be operable at very high-speed. The main requirements for these gain stages are to obtain a gain of more than 1 in a short time while preserving linearity.
Among the broad variety of ADC topologies, ADCs with zero-crossing amplifier units have recently gained attention for use in high-speed high-resolution applications. In particular, applications which require sampling rates of more than 1 GS/s require very fast operating gain stages.
Y. Chu, “A high performance zero-crossing-based pipelined analog-to-digital converter”, http://dspace.mit.edu/bitstream/handle/1721.1/44377/276947916.pdf?sequence=1, DSpace@MIT, discloses a method for dynamically controlling a current source at the output of a zero-crossing amplifier in an analog-to-digital converter for improved linearity. To improve the current source linearity, a dynamic biasing scheme is employed to compensate for its finite output impedance. In particular, it also discloses to generate a dynamic bias voltage to apply to a gate of a MOSFET to compensate for a decreasing ramp rate at an output node. As the output voltage rises, the bias voltage applied to the gate of the MOSFET is reduced, which makes the amount of current sourced by the MOSFET constant and therefore compensates for the reduction in the ramp rate.